Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. Conventional CMOS SRAM cells typically consist of six transistors: two P channel field effect transistors (PFETs) for a pull-up operation, two N channel field effect transistors (NFETs) for pull down, and two NFETs for input/output (i.e., passgate) access. A conventional SRAM array consists of “m” rows and “n” columns of the aforementioned SRAM cells. Cells of the same row share one word line (WL), while cells of the same column share the same bit line pair, e.g., BL and BR.
An SRAM has three different states: standby (the circuit is idle), reading (the data has been requested) and writing (updating the contents). In the standby mode, if the word line is not asserted, access transistors disconnect the cell from the bit lines; while cross-coupled inverters will continue to reinforce each other as long as they are connected to supply. During standby, all the WLs are at low (i.e., at GND level) and all bit lines are biased to the standby voltage level (of the power supply) Vdd. However, in the standby mode, the SRAM cell can exhibit significant passgate leakage. Also, known SRAM cells can exhibit wordline overvoltage stress when the wordline voltage is negative.